The present invention relates to an information processing system and, more particularly, to a cache invalidation control system.
In conventional techniques, an information processing apparatus in which a main memory and an I/O unit or an arithmetic processor (request source of a memory request) operate by asynchronous clocks is available. In such an information processing apparatus, a memory access control unit comprises a first control unit which operates in synchronism with the request source, and a second control unit which operates in synchronism with the main memory. When the request source accesses the main memory, the first control unit accepts the request and stores memory access information in a data buffer predetermined for each request source. The information is stored in the data buffer until it is read out by a read address stored in the first control unit in order to send a processor number which is a part of the memory access information stored in the data buffer or reply information indicating the presence/absence of reply data to an arithmetic processor of the request source after a reply returns in response to the request.
The first control unit sends the request to the second control unit. When the second control unit receives the request, it performs contention control with requests from other request sources. If the request can be processed, the second control unit supplies the read address to the data buffer to read out the memory access information and sends the memory access information with the request to the main memory.
In addition, the second control unit includes a buffer for storing a memory request address which is a part of the memory access information. When the second control unit sends a memory request to the main memory, the type of instruction of the memory request is determined. If the instruction is a store instruction, the memory request addresses of the memory access information are stored in the special buffer in the order that they are sent to the main memory, and a cache invalidation request is issued to the first control unit.
The first control unit receives the cache invalidation request sent from the second control unit and supplies the read address to the buffer of the second control unit in which the memory request address is stored, thereby reading out the memory request address. The first control apparatus sends the cache invalidation request with the readout memory request address to the request source having a cache function.
In the above conventional cache invalidation control system, a special buffer having a capacity capable of storing memory request addresses must be provided in the second control unit in order to invalidate a cache. In addition, since a number of signal lines must be provided to send the memory request addresses from the buffer in the second control unit to the first control unit, the number of signal lines between interfaces is increased, and the amount of hardware required is increased.